EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 56

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.4.3.4 Address calculation
2010-09-06 - d0001_Rev1.00
At the start of a DMA cycle, or 2
memory. After it performs 2
The controller does not support a dst_size value that is different to the src_size value. If it detects a
mismatch in these values, it uses the src_size value for source and destination and when it next updates
the n_minus_1 field, it also sets the dst_size field to the same as the src_size field.
After the controller completes the N transfers it sets the cycle_ctrl field to b000, to indicate that the
channel_cfg data is invalid. This prevents it from repeating the same DMA transfer.
To calculate the source address of a DMA transfer, the controller performs a left shift operation on the
n_minus_1 value by a shift amount that src_inc specifies, and then subtracts the resulting value from the
source data end pointer. Similarly, to calculate the destination address of a DMA transfer, it performs a
left shift operation on the n_minus_1 value by a shift amount that dst_inc specifies, and then subtracts
the resulting value from the destination end pointer.
Depending on the value of src_inc and dst_inc, the source address and destination address can be
calculated using the equations:
src_inc = b00 and dst_inc = b00
src_inc = b01 and dst_inc = b01
src_inc = b10 and dst_inc = b10
src_inc = b11 and dst_inc = b11
Table 8.10 (p. 56) lists the destination addresses for a DMA cycle of six words.
Table 8.10. DMA cycle of six words using a word increment
1
Table 8.11 (p. 57) lists the destination addresses for a DMA transfer of 12 bytes using a halfword
increment.
This value is the result of count being shifted left by the value of dst_inc.
Bit
Initial values of channel_cfg, prior to the DMA cycle
src_size = b10, dst_inc = b10, n_minus_1 = b101, cycle_ctrl = 1
DMA transfers
Final values of channel_cfg, after the DMA cycle
src_size = b10, dst_inc = b10, n_minus_1 = 0, cycle_ctrl = 0
Name
End Pointer
0x2AC
0x2AC
0x2AC
0x2AC
0x2AC
0x2AC
Description
When the controller operates in peripheral scatter-gather mode, you must only use this
value in the alternate data structure.
R
, or N, transfers it stores the updated channel_cfg in system memory.
R
Count
5
4
3
2
1
0
• source address = src_data_end_ptr - n_minus_1
• destination address = dst_data_end_ptr - n_minus_1.
• source address = src_data_end_ptr - (n_minus_1 << 1)
• destination address = dst_data_end_ptr - (n_minus_1 << 1).
• source address = src_data_end_ptr - (n_minus_1 << 2)
• destination address = dst_data_end_ptr - (n_minus_1 << 2).
• source address = src_data_end_ptr
• destination address = dst_data_end_ptr.
DMA transfer, the controller fetches the channel_cfg from system
Difference
0x14
0x10
0xC
0x8
0x4
0x0
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56
1
Address
0x298
0x29C
0x2A0
0x2A4
0x2A8
0x2AC
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