EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 303

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.5.9 LETIMERn_IF - Interrupt Flag Register
21.5.10 LETIMERn_IFS - Interrupt Flag Set Register
7:0
31:5
4
3
2
1
0
31:5
4
3
2
Bit
Offset
0x020
Reset
Access
Name
Bit
Offset
0x024
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
REP1
Optional repeat counter or buffer for REP0
Reserved
REP1
Set when repeat counter 1 reaches zero.
REP0
Set when repeat counter 0 reaches zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag.
UF
Set on LETIMER underflow.
COMP1
Set when LETIMER reaches the value of COMP1
COMP0
Set when LETIMER reaches the value of COMP0
Reserved
REP1
Write to 1 to set the REP1 interrupt flag.
REP0
Write to 1 to set the REP0 interrupt flag.
UF
Write to 1 to set the UF interrupt flag.
Name
Name
Name
0x00
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
R
R
R
R
R
W1
W1
W1
Access
Access
Access
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303
Bit Position
Bit Position
Repeat Counter 1
Repeat Counter 1 Interrupt Flag
Repeat Counter 0 Interrupt Flag
Underflow Interrupt Flag
Compare Match 1 Interrupt Flag
Compare Match 0 Interrupt Flag
Set Repeat Counter 1 Interrupt Flag
Set Repeat Counter 0 Interrupt Flag
Set Underflow Interrupt Flag
Description
Description
Description
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