EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 54

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-09-06 - d0001_Rev1.00
Bit
[27:26]
[25:24]
[23:21]
[20:18]
[17:14]
Name
src_inc
src_size
dst_prot_ctrl
src_prot_ctrl
R_power
Description
Note
Set the bits to control the source address increment. The address increment depends on the
source data width as follows:
Source data width = byte
Source data width = halfword
Source data width = word
Set the bits to match the size of the source data:
b00 = byte
b01 = halfword
b10 = word
b11 = reserved.
Set the bits to control the state of HPROT when the controller writes the destination data.
Bit [23]
Bit [22]
Bit [21]
Set the bits to control the state of HPROT when the controller reads the source data.
Bit [20]
Bit [19]
Bit [18]
Set these bits to control how many DMA transfers can occur before the controller rearbitrates.
The possible arbitration rate settings are:
b0000
b0001
b0010
b0011
b0100
b0101
b0110
b0111
b1000
b1001
b1010 - b1111
You must set dst_size to contain the same value that src_size contains.
This bit has no effect on the DMA.
This bit has no effect on the DMA.
Controls the state of HPROT as follows:
0 = HPROT is LOW and the access is non-privileged.
1 = HPROT is HIGH and the access is privileged.
This bit has no effect on the DMA.
This bit has no effect on the DMA.
Controls the state of HPROT as follows:
0 = HPROT is LOW and the access is non-privileged.
1 = HPROT is HIGH and the access is privileged.
Arbitrates after each DMA transfer.
Arbitrates after 2 DMA transfers.
Arbitrates after 4 DMA transfers.
Arbitrates after 8 DMA transfers.
Arbitrates after 16 DMA transfers.
Arbitrates after 32 DMA transfers.
Arbitrates after 64 DMA transfers.
Arbitrates after 128 DMA transfers.
Arbitrates after 256 DMA transfers.
Arbitrates after 512 DMA transfers.
Arbitrates after 1024 DMA transfers. This means that no arbitration occurs
during the DMA transfer because the maximum transfer size is 1024.
b00 = byte.
b01 = halfword.
b10 = word.
b11 = no increment. Address remains set to the value that
the src_data_end_ptr memory location contains.
b00 = reserved.
b01 = halfword.
b10 = word.
b11 = no increment. Address remains set to the value that
the src_data_end_ptr memory location contains.
b00 = reserved.
b01 = reserved.
b10 = word.
b11 = no increment. Address remains set to the value that
the src_data_end_ptr memory location contains.
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