EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 211

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.19 USARTn_IFC - Interrupt Flag Clear Register
16.5.20 USARTn_IEN - Interrupt Enable Register
31:13
12
11
10
9
8
7
6
5
4
3
2:1
0
Offset
0x048
Reset
Access
Name
Bit
Offset
0x04C
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
Reserved
CCF
Write to 1 to clear the CCF interrupt flag.
SSM
Write to 1 to clear the SSM interrupt flag.
MPAF
Write to 1 to clear the MPAF interrupt flag.
FERR
Write to 1 to clear the FERR interrupt flag.
PERR
Write to 1 to clear the PERR interrupt flag.
TXUF
Write to 1 to clear the TXUF interrupt flag.
TXOF
Write to 1 to clear the TXOF interrupt flag.
RXUF
Write to 1 to clear the RXUF interrupt flag.
RXOF
Write to 1 to clear the RXOF interrupt flag.
RXFULL
Write to 1 to clear the RXFULL interrupt flag.
Reserved
TXC
Write to 1 to clear the TXC interrupt flag.
Name
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Access
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211
Bit Position
Bit Position
Clear Collision Check Fail Interrupt Flag
Clear Slave-Select In Master Mode Interrupt Flag
Clear Multi-Processor Address Frame Interrupt Flag
Clear Framing Error Interrupt Flag
Clear Parity Error Interrupt Flag
Clear TX Underflow Interrupt Flag
Clear TX Overflow Interrupt Flag
Clear RX Underflow Interrupt Flag
Clear RX Overflow Interrupt Flag
Clear RX Buffer Full Interrupt Flag
Clear TX Complete Interrupt Flag
Description
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