EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 335

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

24.4 Register Map
24.5 Register Description
24.5.1 VCMP_CTRL - Control Register
31
30
29:28
27:24
23:18
17
16
15:11
10:8
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
Reserved
HALFBIAS
Set this bit to 1 to halve the bias current. Table 24.1 (p. 332) .
Reserved
BIASPROG
These bits control the bias current level. Table 24.1 (p. 332) .
Reserved
IFALL
Set this bit to 1 to set the EDGE interrupt flag on falling edges of comparator output.
IRISE
Set this bit to 1 to set the EDGE interrupt flag on rising edges of comparator output.
Reserved
WARMTIME
Set warm-up time
Name
Value
0
1
2
3
4
5
6
Name
VCMP_CTRL
VCMP_INPUTSEL
VCMP_STATUS
VCMP_IEN
VCMP_IF
VCMP_IFS
VCMP_IFC
Mode
4CYCLES
8CYCLES
16CYCLES
32CYCLES
64CYCLES
128CYCLES
256CYCLES
1
0x7
0
0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
Access
Description
4 HFPERCLK cycles
8 HFPERCLK cycles
16 HFPERCLK cycles
32 HFPERCLK cycles
64 HFPERCLK cycles
128 HFPERCLK cycles
256 HFPERCLK cycles
...the world's most energy friendly microcontrollers
335
Bit Position
Type
RW
RW
R
RW
R
W1
W1
Half Bias Current
VCMP Bias Programming Value
Falling Edge Interrupt Sense
Rising Edge Interrupt Sense
Warm-Up Time
Description
Description
Control Register
Input Selection Register
Status Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
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