EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 198

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

27:26
25
24
23
22
21
20
19
18
17
16
15
14
Bit
2010-09-06 - d0001_Rev1.00
TXDELAY
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Reserved
ERRSTX
When set, the transmitter is disabled on framing and parity errors (asynchronous mode only) in the receiver.
ERRSRX
When set, the receiver is disabled on framing and parity errors (asynchronous mode only).
ERRSDMA
When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only).
BIT8DV
The default value of the 9th bit. If 9-bit frames are used, and an 8-bit write operation is done, leaving the 9th bit unspecified, the
9th bit is set to the value of BIT8DV.
SKIPPERRF
When set, the receiver discards frames with parity errors (asynchronous mode only). The PERR interrupt flag is still set.
SCRETRANS
When in SmartCard mode, a NACK'ed frame will be kept in the shift register and retransmitted if the transmitter is still enabled.
SCMODE
Use this bit to enable or disable SmartCard mode.
AUTOTRI
When enabled, TXTRI is set by hardware whenever the transmitter is idle, and TXTRI is cleared by hardware when transmission starts.
AUTOCS
When enabled, the output on USn_CS will be activated one baud-period before transmission starts, and deactivated when
transmission ends.
CSINV
Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave.
TXINV
The output from the USART transmitter can optionally be inverted by setting this bit.
Name
Value
0
1
2
3
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Value
0
1
Mode
NONE
SINGLE
DOUBLE
TRIPLE
Description
Received framing and parity errors have no effect on transmitter
Received framing and parity errors disable the transmitter
Description
Framing and parity errors have no effect on receiver
Framing and parity errors disable the receiver
Description
Framing and parity errors have no effect on DMA requests from the USART
DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set
Description
The output on U(S)n_TX when the transmitter is idle is defined by TXINV
U(S)n_TX is tristated whenever the transmitter is idle
Description
Chip select is active low
Chip select is active high
0x0
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Description
Frames are transmitted immediately
Transmission of new frames are delayed by a single baud period
Transmission of new frames are delayed by two baud periods
Transmission of new frames are delayed by three baud periods
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198
TX Delay Transmission
Disable TX On Error
Disable RX On Error
Halt DMA On Error
Bit 8 Default Value
Skip Parity Error Frames
SmartCard Retransmit
SmartCard Mode
Automatic TX Tristate
Automatic Chip Select
Chip Select Invert
Transmitter output Invert
Description
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