EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 210

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.18 USARTn_IFS - Interrupt Flag Set Register
3
2
1
0
31:13
12
11
10
9
8
7
6
5
4
3
2:1
0
Bit
Offset
0x044
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.
RXFULL
Set when the receive buffer becomes full.
RXDATAV
Set when data becomes available in the receive buffer.
TXBL
Set when buffer becomes empty if TXBIL is set, or when buffer goes from full to half-full if TXBIL is cleared
TXC
This interrupt is used after a transmission when both the TX buffer and shift register are empty.
Reserved
CCF
Write to 1 to set the CCF interrupt flag.
SSM
Write to 1 to set the SSM interrupt flag.
MPAF
Write to 1 to set the MPAF interrupt flag.
FERR
Write to 1 to set the FERR interrupt flag.
PERR
Write to 1 to set the PERR interrupt flag.
TXUF
Write to 1 to set the TXUF interrupt flag.
TXOF
Write to 1 to set the TXOF interrupt flag.
RXUF
Write to 1 to set the RXUF interrupt flag.
RXOF
Write to 1 to set the RXOF interrupt flag.
RXFULL
Write to 1 to set the RXFULL interrupt flag.
Reserved
TXC
Write to 1 to set the TXC interrupt flag.
Name
Name
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Access
Access
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210
Bit Position
RX Buffer Full Interrupt Flag
RX Data Valid Interrupt Flag
TX Buffer Level Interrupt Flag
TX Complete Interrupt Flag
Set Collision Check Fail Interrupt Flag
Set Slave-Select in Master mode Interrupt Flag
Set Multi-Processor Address Frame Interrupt Flag
Set Framing Error Interrupt Flag
Set Parity Error Interrupt Flag
Set TX Underflow Interrupt Flag
Set TX Overflow Interrupt Flag
Set RX Underflow Interrupt Flag
Set RX Overflow Interrupt Flag
Set RX Buffer Full Interrupt Flag
Set TX Complete Interrupt Flag
Description
Description
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