EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 63

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.7.7 DMA_CHUSEBURSTS - Channel Useburst Set Register
8.7.8 DMA_CHUSEBURSTC - Channel Useburst Clear Register
31:8
7
6
5
4
3
2
1
0
Offset
0x018
Reset
Access
Name
Bit
Offset
0x01C
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
Reserved
CH7USEBURSTS
See description for channel 0.
CH6USEBURSTS
See description for channel 0.
CH5USEBURSTS
See description for channel 0.
CH4USEBURSTS
See description for channel 0.
CH3USEBURSTS
See description for channel 0.
CH2USEBURSTS
See description for channel 0.
CH1USEBURSTS
See description for channel 0.
CH0USEBURSTS
Write to 1 to enable the useburst setting for this channel. Reading returns the useburst status. After the penultimate 2^R transfer
completes, if the number of remaining transfers, N, is less than 2^R then the controller resets the chnl_useburst_set bit to 0.
This enables you to complete the remaining transfers using dma_req[] or dma_sreq[]. In peripheral scatter-gather mode, if the
next_useburst bit is set in channel_cfg then the controller sets the chnl_useburst_set[C] bit to a 1, when it completes the DMA cycle
that uses the alternate data structure.
Name
Value
0
1
Mode
SINGLEANDBURST
BURSTONLY
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW1
RW1
RW1
RW1
RW1
RW1
RW1
RW1
Access
Description
Channel responds to both single and burst requests
Channel responds to burst requests only
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Bit Position
Bit Position
63
Channel 7 Useburst Set
Channel 6 Useburst Set
Channel 5 Useburst Set
Channel 4 Useburst Set
Channel 3 Useburst Set
Channel 2 Useburst Set
Channel 1 Useburst Set
Channel 0 Useburst Set
Description
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