EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 272

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.5.18 TIMERn_DTFC - DTI Fault Configuration Register
7:4
3:0
31:28
27
26
25
24
23:18
17:16
Bit
Offset
0x078
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Set time span for the rising edge.
Reserved
DTPRESC
Select prescaler for DTI.
Reserved
DTLOCKUPFEN
Set this bit to 1 to enable core lockup as a fault source
DTDBGFEN
Set this bit to 1 to enable debugger as a fault source
DTPRS1FEN
Set this bit to 1 to enable PRS source 1(PRS channel determined by DTPRS1FSEL) as a fault source
DTPRS0FEN
Set this bit to 1 to enable PRS source 0(PRS channel determined by DTPRS0FSEL) as a fault source
Reserved
DTFA
Select fault action.
Name
Name
Value
DTRISET
Value
0
1
2
3
4
5
6
7
8
9
10
Value
0
1
2
Mode
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1024
Mode
NONE
INACTIVE
CLEAR
0x0
0
0
0
0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Description
Rise time of DTRISET+1 prescaled HFPERCLK cycles
Description
The HFPERCLK is undivided
The HFPERCLK is divided by 2
The HFPERCLK is divided by 4
The HFPERCLK is divided by 8
The HFPERCLK is divided by 16
The HFPERCLK is divided by 32
The HFPERCLK is divided by 64
The HFPERCLK is divided by 128
The HFPERCLK is divided by 256
The HFPERCLK is divided by 512
The HFPERCLK is divided by 1024
Description
No action on fault
Set outputs inactive
Clear outputs
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272
Bit Position
DTI Prescaler Setting
DTI Lockup Fault Enable
DTI Debugger Fault Enable
DTI PRS 1 Fault Enable
DTI PRS 0 Fault Enable
DTI Fault Action
Description
Description
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