EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 416

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.3.3.3 Waveforms with 1/3 Bias and Duplex Multiplexing
2010-09-06 - d0001_Rev1.00
Figure 29.10. LCD 1/2 Bias and Duplex Multiplexing - LCD_SEG0-LCD_COM1
In this mode, each frame is divided into 4 periods. LCD_COM[1:0] lines can be multiplexed with all
segment lines. Figures show 1/3 bias and duplex multiplexing (waveforms show two frames).
Figure 29.11. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM0
Figure 29.12. LCD 1/3 Bias and Duplex Multiplexing - LCD_COM1
1/3 bias and duplex multiplexing - LCD_SEG0
The LCD_SEG0 waveform on the left is just an example to illustrate how different segment waveforms
can be multiplexed with the COM lines in order to turn on and off LCD pixels. As illustrated in the
figures below, this waveform will turn ON pixels connected to LCD_COM0, while pixels connected to
LCD_COM1 will be turned OFF.
Figure 29.13. LCD 1/3 Bias and Duplex Multiplexing - LCD_SEG0
-V
V
V
V
V
V
V
V
LC1
LC2
LC1
LC2
LC1
LC2
LC1
LC1
-V
V
V
V
V
V
V
V
V
LC0
(2/3V
LC0
(2/3V
LC0
(2/3V
(1/3V
(1/3V
(1/3V
(1/2V
LC0
LC0
(1/2V
LC3
LC3
LC3
LC3
(V
(V
(V
(V
(V
(V
(V
(V
(V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Fram e Start
SS
Fram e Start
SS
Fram e Start
SS
Fram e Start
LCD
SS
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
)
Fram e End
Fram e End
Fram e End
Fram e End
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