EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 235

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register
(Async Reg)
18.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg)
13:9
8:0
31:16
15
14
13
12:9
8:0
Bit
Offset
0x024
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
For more information about Asynchronous Registers please see Section 5.3 (p. 18) .
Reserved
RXDATAP
Use this register to access data read from the LEUART.
Reserved
RXENAT
Set to enable reception after transmission.
TXDISAT
Set to disable transmitter directly after transmission has competed.
TXBREAK
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the value
of TXDATA.
Reserved
TXDATA
Use this register to write data to the LEUART. If the transmitter is enabled, a transfer will be initiated at the first opportunity.
Name
Name
Value
0
1
Value
0
1
Value
0
1
Description
-
The receiver is enabled, setting RXENS after the frame has been transmitted
Description
-
The transmitter is disabled, clearing TXENS after the frame has been transmitted
Description
The specified number of stop-bits are transmitted
Instead of the ordinary stop-bits, 0 is transmitted to generate a break. A single stop-bit is generated after the break to
allow the receiver to detect the start of the next frame
0x000
0
0
0
0x000
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
W
W
W
W
Access
Access
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235
Bit Position
RX Data Peek
Enable RX After Transmission
Disable TX After Transmission
Transmit Data As Break
TX Data
Description
Description
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