EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 202

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.5.4 USARTn_CMD - Command Register
31:12
11
10
9
8
7
6
5
4
3
2
1
0
Offset
0x00C
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
CLEARRX
Set to clear receive buffer and the RX shift register.
CLEARTX
Set to clear transmit buffer and the TX shift register.
TXTRIDIS
Disables tristating of the transmitter output.
TXTRIEN
Tristates the transmitter output.
RXBLOCKDIS
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
RXBLOCKEN
Set to set RXBLOCK, resulting in all incoming frames being discarded.
MASTERDIS
Set to disable master mode, clearing the MASTER status bit and putting the USART in slave mode.
MASTEREN
Set to enable master mode, setting the MASTER status bit. Master mode should not be enabled while TXENS is set to 1. To enable
both master and TX mode, write MASTEREN before TXEN, or enable them both in the same write operation.
TXDIS
Set to disable transmission.
TXEN
Set to enable data transmission.
RXDIS
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
RXEN
Set to activate data reception on U(S)n_RX.
Name
0
0
0
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
Access
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202
Bit Position
Clear RX
Clear TX
Transmitter Tristate Disable
Transmitter Tristate Enable
Receiver Block Disable
Receiver Block Enable
Master Disable
Master Enable
Transmitter Disable
Transmitter Enable
Receiver Disable
Receiver Enable
Description
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