HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 81

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. The M, Q, S, and T bits can be set/cleared by the user mode specific instructions.
Save Status Register (SSR): The save status register (SSR) can be accessed only in privileged
mode. Before entering the exception handling state, the contents of SR are saved. At a reset, the
SSR initial value is undefined.
Save Program Counter (SPC): The save program counter (SPC) can be accessed only in
privileged mode. Before entering the exception handling state, the contents of PC are saved. At a
reset, the SPC initial value is undefined.
Bit
9
8
7
6
5
4
3, 2
1
0
2. When DSP is used, this bit is extended. Refer to section 3.2.3, CPU Register Sets.
Bit Name
M
Q
I3
I2
I1
I0

S
T
Other bits can be read or written in privileged mode.
Initial
Value


1
1
1
1
All 0


R/W Description
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W Saturation Mode*
R/W T Bit*
M Bit*
Q Bit*
These bits are used by the DIV0S, DIV0U, and DIV1
instructions. These bits can be changed even in user mode
by executing these instructions. These bits are undefined at
a reset. These bits do not change in an exception handling
state.
Interrupt Mask Bits
The 4-bit data indicates the interrupt mask level. These bits
do not change even if an interrupt occurs. At a reset, these
bits are initialized to B’1111. These bits are not affected in
an exception handling state.
Reserved*
These bits are always read as 0. The write value should
always be 0. When 1 is written to these bits, operation
cannot be guaranteed.
Specifies saturation mode for multiply instructions or multiply
and accumulate instructions. This bit can be specified by the
SETS and CLRS instructions in user mode.
At a reset, this bit is undefined. This bit is not affected in an
exception handling state.
Indicates true or false for compare instructions or carry or
borrow occurrence for an operation instruction with carry or
borrow. This bit can be specified by the SETT and CLRT
instructions in user mode.
At a reset, this bit is undefined. This bit is not affected in an
exception handling state.
1
1
1
2
1
Rev. 1.00, 02/04, page 43 of 804