HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 149

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

The DSR is assigned to the system registers. For the DSR, the following load and store
instructions are supported.
If the DSR is read by the STS instruction, upper bits (bits 31 to 16) are all 0
3.5.2
DSP instructions are instructions for digital signal processing performed by the DSP unit. These
instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel.
The instruction code is divided into an A field and B field; a parallel data transfer instruction is
specified in the A field, and a single or double data operation instruction in the B field.
Instructions can be specified independently, and are also executed independently.
B-field data operation instructions are of three kinds: double data operation instructions,
conditional single data operation instructions, and unconditional single data operation instructions.
The formats of the DSP operation instructions are shown in table 3.17. The respective operands
are selected independently from the DSP registers. The correspondence between DSP instruction
operands and registers is shown in table 3.18.
Parallel processing only instructions in the A field (without those in the B field) can be executed
(transferring data in parallel without DSP data operation instructions).
Bits
0
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
Bit Name
DC
DSP Instruction Set
Initial
Value
0
R/W
R/W
Function
DSP Status Bit
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status has not occurred (false)
1: Designated mode status has occurred
Indicates the operation result by carry or borrow
regardless of the CS bit status after the PADDC or
PSUBC instruction has been executed.
Rev. 1.00, 02/04, page 111 of 804