HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 169

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand
and the destination operand. The lower word and guard-bit parts are ignored for the source
operand and those of the destination operand are automatically cleared as in the ALU logical
operations. The shift amount is specified by the source 2 operand as an integer data. The source 2
operand can be specified by either the register or immediate operand. The available shift range is
from –16 to +16. Here, a negative value means the right shift, and a positive value means the left
shift. It is possible for any source 2 operand to specify from –32 to +31, but the result is unknown
if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the
source 1 operand must be the same register as the destination’s. These operations are executed in
the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which
memory access is performed.
Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated even though the specified condition is true and the operation is executed. In case of an
unconditional operation, they are always updated in accordance with the operation result. The
definition of the DC bit is selected by the CS[2:0] (DC bit condition selection) bits in DSR. The
DC bit result is:
1. Carry or Borrow Mode: CS[2:0] = B'000
2. Negative Value Mode: CS[2:0] = B'001
3. Zero Value Mode: CS[2:0] = B'010
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The DC bit indicates the last shifted out data as the operation result.
Bit 31 of the operation result is loaded into the DC bit.
The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0.
Shift out
Cleared to 0
Shift amount data
32 31
(source 2)
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Left shift
16 15
32 31
Figure 3.18 Logical Shift Operation Flow
0
> = 0
+16 to -16
22 21 16
5
Imm2
0
Sy
< 0
0
15
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Updated
0
0
32 31
Rev. 1.00, 02/04, page 131 of 804
DSR
Shift out
Ignored
Right shift
16 15
GT
Z
N
V DC
0