HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 262

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
9.3.4
The data bus width of areas 3 and 4 is set 8 bits or 16 bits by the CSn space bus control register
(CSnBCR, n = 3 or 4). The data bus width of area 0 is fixed 16 bits. For details, see section 9.4.2,
CSn Space Bus Control Register.
9.4
The BSC has the following registers. Refer to section 27, List of Registers, for the register
addresses and the register states in each operating mode.
Do not access spaces other than CS0 until the termination of the setting the memory interface.
When accessing spaces other than CS0, set the CSn space bus control register (CSnBCR) which
corresponds to the area to be accessed before setting the CSn space wait control register
(CSnWCR).
• Common control register (CMNCR)
• CS0 space bus control register (CS0BCR)
• CS3 space bus control register (CS3BCR)
• CS4 space bus control register (CS4BCR)
• CS0 space wait control register (CS0WCR)
• CS3 space wait control register (CS3WCR)
• CS4 space wait control register (CS4WCR)
• SDRAM control register (SDCR)
• Refresh timer control/status register (RTCSR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
• Reset wait counter (RWTCNT)
• SDRAM mode register for CS3 space (SDMR3)*
Note: * Substance of this register is in the SDRAM, and can be written to by accessing the area
Rev. 1.00, 02/04, page 224 of 804
Data Bus Width
Register Descriptions
of this register. For details, see Power-On Sequence in section 9.5.5, SDRAM
Interface.

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