HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 439

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

15.3.9
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
Bit
2
1
0
Bit
15
14
13
Bit Name
TFUDFE
RFUDFE
RFOVFE
Bit Name
TFWM2
TFWM1
TFWM0
FIFO Control Register (SIFCTR)
0
Initial
Value
0
0
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit FIFO Underflow Enable
0: Disables interrupts due to transmit FIFO underflow
1: Enables interrupts due to transmit FIFO underflow
Receive FIFO Underflow Enable
0: Disables interrupts due to receive FIFO underflow
1: Enables interrupts due to receive FIFO underflow
Receive FIFO Overflow Enable
0: Disables interrupts due to receive FIFO overflow
1: Enables interrupts due to receive FIFO overflow
Description
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 4 or more stages of
111: Issue a transfer request when 1 or more stages of
•
•
A transfer request to the transmit FIFO is issued by
the TDREQE bit in SISTR.
The transmit FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
transmit FIFO are empty.
Rev. 1.00, 02/04, page 401 of 804