HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 249

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

8.4
There are three types of interrupt sources: NMI, IRQ, and on-chip peripheral modules. Each
interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks
an interrupt, so the interrupt request is ignored.
8.4.1
The NMI interrupt has the highest priority level of 16. When the BL bit in the status register (SR)
is 0, NMI interrupts are accepted. NMI interrupts are edge-detected. In sleep or standby mode, the
interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the interrupt
control register 0 (ICR0) is used to select either rising or falling edge detection.
When using edge-input detection for NMI interrupts, a pulse width of at least two Pφ cycles
(peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt
mask level bits (I3 to I0) in the status register (SR).
It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt.
8.4.2
IRQ interrupts are input by level or edge from pins IRQ7, IRQ4 to IRQ0. The priority level can be
set by interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When the ICR1 and ICR2 registers are rewritten, IRQ interrupts may be mistakenly detected,
depending on the IRQ pin states. To prevent this, rewrite the register while interrupts are masked,
then release the mask after clearing the illegal interrupt by writing 0 to IRR0 after reading IRR0.
Edge input interrupt detection requires input of a pulse width of more than two cycles on a
peripheral clock (Pφ) basis.
When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU
samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt
handling.
Interrupt Sources
NMI Interrupt
IRQ Interrupts
Rev. 1.00, 02/04, page 211 of 804