HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 609

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.18 EP6 Receive Data Size Register (EPSZ6)
EPSZ6 is a receive data size resister for endpoint 6. EPSZ6 indicates the number of bytes received
from the host. FIFO of endpoint 6 has a dual-buffer configuration. The size of the received data
indicated by this register is the size of the currently selected side (can be read by CPU).
20.3.19 Trigger Register (TRG)
TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2i, EP2o,
EP4, EP5, and EP6. The packet enable trigger for the IN FIFO register and read complete trigger
for the OUT FIFO register are triggers to be given. If a bit corresponding to each endpoint is set to
1, a trigger is given. Each bit in this register is automatically cleared to 0 after it is set to 1.
Bit
7 to 0
Bit
15
14
13
12
11 to 7 
6
5
4
3
2
1
0
Bit Name
—
Bit Name

EP6 RDFN
EP5 PKTE
EP4 PKTE
EP2o RDFN 0
EP2i PKTE
EP1 PKTE

EP0s RDFN 1
EP0o RDFN 0
EP0i PKTE
Initial Value
All 0
Initial Value
0
0
0
0
All 0
0
0
0
0
R/W
R
R/W

W
W
W

W
W
W

W
W
W
EP2i Packet Enable
EP0i Packet Enable
Description
Number of received bytes for endpoint 6
Description
Reserved
The write value should always be 0. If 1 is written
to this bit, correct operation cannot be
guaranteed.
EP6 Read Complete
EP5 Packet Enable
EP4 Packet Enable
Reserved
The write value should always be 0. If 1 is written
to these bits, correct operation cannot be
guaranteed.
EP2o Read Complete
EP1 Packet Enable
Reserved
The write value should always be 0. If 1 is written
to this bit, correct operation cannot be
guaranteed.
EP0s Read Complete
EP0o Read Complete
Rev. 1.00, 02/04, page 571 of 804