HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 235

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3
7.3.1
In the event of simultaneous accesses to the same page from different buses, the conflict on the
pages occurs. Although each access is completed correctly, this kind of conflict tends to lower U
memory accessibility. Therefore it is advisable to provide software measures to prevent such
conflict as far as possible. For example, conflict will not arise if different memory or different
pages are accessed by each bus.
7.3.2
The I bus is shared by several bus master modules. When the U memory is accessed via the I bus,
a conflict between the other I-bus master modules may occur on the I bus. This kind of conflict
tends to lower U memory accessibility. Therefore it is advisable to provide software measures to
prevent such conflict as far as possible. For example, by accessing the U memory by the CPU not
via the I bus but from space P2 or Uxy via the L bus, conflict on the I bus can be prevented.
7.3.3
When the U memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the U memory is accessed while the cache is enabled
(CCR1.CR = 1), it is advisable to access the U memory via the L bus from space P2 or Uxy. In a
program that requires high performance, it is advisable to access the U memory from space P2 or
Uxy.
The relationship described above is summarized in table 7.2.
Table 7.2
Note:
Setting
CCR1.CE
0
1
A: Enabled (recommended)
B: Enabled
X: Disabled
Usage Notes
Page Conflict
Bus Conflict
Cache Settings
Cache Settings
P0, U0
B
X
Address Space and Access Enabled or Disabled
Rev. 1.00, 02/04, page 197 of 804
P2, Uxy
A
A