HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 330

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even
when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be
performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot
be immediately determined whether or not bus mastership has been released by looking at the CSn
signal or other bus control signals. The states that do not allow bus mastership release are shown
below.
1. 16-byte transfer because of a cache miss
2. During copyback operation for the cache
3. Between the read and write cycles of a TAS instruction
4. Multiple bus cycles generated when the data bus width is smaller than the access size (for
5. 16-byte transfer by the DMAC
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
Master Mode: In master mode, the LSI has the bus mastership until a bus request is received from
another device. Upon acknowledging the assertion (low level) of the external bus request signal
BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK
signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the
slave has released the bus, it negates the BACK signal and resumes the bus usage.
The SDRAM issues all bank pre-charge commands (PALLs) when active banks exist and releases
the bus after completion of a PALL command.
The bus sequence is as follows.
1. The address bus and data bus are placed in a high-impedance state synchronized with the rising
2. The bus mastership enable signal is asserted 0.5 cycles after the above timing, synchronized
3. The bus control signals (BS, CSn, RAS, CAS, WEn/DQMn, RD, and RD/WR) are placed in
4. Bus request signals are sampled at the falling edge of CKIO.
The sequence for reclaiming the bus mastership from a slave is described below.
Rev. 1.00, 02/04, page 292 of 804
example, between bus cycles when longword access is made to a memory with a data bus
width of 8 bits)
edge of CKIO.
with the falling edge of CKIO.
the high-impedance state at subsequent rising edges of CKIO. These bus control signals go
high one cycle before being placed in the high-impedance state.