HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 163

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

3.5.6
Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixed-
point arithmetic operations as shown in table 3.21.
The ALU logical operation is executed between registers. Each source operand and destination
operand is selected independently from one of the DSP registers. As shown in figure 3.15, this
type of operation uses only the upper word of each operand. The lower word and guard-bit parts
are ignored for the source operand and those of the destination operand are automatically cleared.
These operations are also executed in the DSP stage, as shown in figure 3.10. The DSP stage is the
same stage as the MA stage in which memory access is performed.
Table 3.24 Variation of ALU Logical Operations
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of the DC bit is selected by the CS[2:0] (DC bit condition
selection) bits in DSR. The DC bit result is:
Mnemonic
PAND
POR
PXOR
ALU Logical Operations
39
31
Source 1
Function
Logical AND
Logical OR
Logical exclusive OR
Figure 3.15 ALU Logical Operation Flow
16
39
31
0
ALU
39
16
Source 1
Sx
Sx
Sx
Destination
31
Source 2
0
16
DSR
Source 2
Sy
Sy
Sy
Rev. 1.00, 02/04, page 125 of 804
Ignored
Cleared to 0
0
GT Z
N
V DC
Destination
Dz
Dz
Dz