HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 216

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is
valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in write-
back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The tag address
holds the physical address used in the external memory access. It is composed of 22 bits (address
bits 31 to10 for memory access) used for comparison during cache searches.
In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus
State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units
(16 bytes). The data array is not initialized by a power-on or manual reset.
LRU: With the 4-way set associative system, up to four instructions or data with the same entry
address can be registered in the cache. When an entry is registered, LRU shows which of the four
ways it is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used
(LRU) algorithm is used to select the way.
Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 5.1 shows the
relationship between the LRU bits and the way to be replaced when the cache locking mechanism
is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section
5.2.2, Cache Control Register 2.) If a bit pattern other than those listed in table 5.1 is set in the
LRU bits by software, the cache will not function correctly. When modifying the LRU bits by
software, set one of the patterns listed in table 5.1.
The LRU bits are initialized to B'000000 by a power-on reset, but are not initialized by a manual
reset.
Table 5.1
Rev. 1.00, 02/04, page 178 of 804
LRU (Bits 5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
LRU and Way Replacement (when Cache Locking Mechanism is Disabled)
Way to be Replaced
3
2
1
0