HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 72

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

2.2.3
The physical address space is divided into eight areas as shown in figure 2.5. Area 1 is used as the
on-chip I/O space, and most of the on-chip registers of this LSI are mapped to this area*. In this
LSI, areas 2 and 5 to 7 are reserved areas. The remaining three areas, areas 0, 3, and 4, are used as
the external address space. Each area of the external address space can be connected to different
types of memory (for details, see section 9, Bus State Controller (BSC)).
The upper three bits of a logical address are normally masked from the CPU and treated as a
shadow. In privileged mode, for example, logical addresses H'00000100 in the P0 area,
H'80000100 in the P1 area, H'A0000100 in the P2 area, and H'C0000100 in the P3 area are all
mapped to the same external address H'00000100 in area 0. However, since addresses cannot be
mapped to the P4 area, the external address space cannot be accessed by an access to the P4 area.
The three areas (areas 0, 3, and 4) to which the external memory can be connected are each a 64-
Mbyte external address space. Since this LSI has 24 address pins, a maximum of 16 Mbytes of
memory can be mounted for each area. Figure 2.5 shows the mounted space corresponding to area
0.
Note: * To access an on-chip I/O register mapped to area 1 of the external address space, make
Rev. 1.00, 02/04, page 34 of 804
External Address Space
an access from the P2 area of the logical address space that is not cacheable.
Figure 2.4 Physical Address Space
H'00000000
H'20000000
H'40000000
H'60000000
H'80000000
H'A0000000
H'C0000000
H'E0000000
H'FFFFFFFF
Shadow space for 29-bit
Shadow space for 29-bit
Shadow space for 29-bit
Shadow space for 29-bit
Shadow space for 29-bit
Shadow space for 29-bit
physical address space
physical address space
physical address space
physical address space
physical address space
physical address space
physical address space
29-bit (512-Mbyte)
On-chip I/O area