HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 628

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Data Stage (Control-Out):
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is out-
transfer, the application waits for data from the host, and after data is received (IFR0/EP0o TS =
1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties
the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
Rev. 1.00, 02/04, page 590 of 804
Data reception from host
OUT token reception
OUT token reception
(IFR0/EP0o TS = 1)
Set EP0o reception
USB function
to TRG/EP0s
complete flag
to TRG/EP0o
Figure 20.9 Data Stage (Control-Out) Operation
1 written
1 written
RDFN?
RDFN?
Yes
Yes
ACK
NACK
NACK
No
No
Interrupt request
receive data size register
data register (EPDR0o)
(TRG/EP0o RDFN = 1)
Read data from EP0o
Read data from EP0o
Clear EP0o reception
Write 1 to EP0o read
(IFR0/EP0o TS = 0)
complete flag
Application
complete bit
(EPSZ0o)