HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 612

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

20.3.23 Endpoint Stall Register (EPSTL)
EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake
to the host from the next transfer when 1 is written to. The stall bit for endpoint 0 is cleared
automatically on reception of 8 byte command data for which decoding is performed by the
function and the EP0 STL bit is cleared. When the SETUPTS bit in IFR0 is set to 1, a write of the
EP0 STL bit to 1 is ignored. For detailed operation, see section 20.6, Stall Operations.
Rev. 1.00, 02/04, page 574 of 804
Bit
4
3
2
1
0
Bit
15 to 11 
10
9
8
7
6
Bit Name
EP5 DMAS
EP2o DMAE
EP2o DMAS
EP2i DMAE
EP2i DMAS
Bit Name
EP6 STL
EP5 STL
EP4 STL

EP3o STL
Initial Value
0
0
0
0
0
Initial
Value
All 0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct
operation cannot be guaranteed.
EP6 Stall
Sets EP6 stall
EP5 Stall
Sets EP5 stall
EP4 Stall
Sets EP4 stall
Reserved
This bit is always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation
cannot be guaranteed.
EP3o Stall
Sets EP3o stall
Description
EP5DMA Request Select
Selects DMA transfer request output for EP5.
EP2oDMA Enable
Enables DMA transfer for EP2o.
EP2oDMA Request Select
Selects DMA transfer request output for EP2o.
EP2iDMA Enable
Enables DMA transfer for EP2i.
EP2iDMA Request Select
Selects DMA transfer request output for EP2i.