HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 271

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

• CS3WCR
Bit
31 to 21
20
19 to 11
10
9
8
7
Bit Name

BAS

WR3
WR2
WR1
WR0
Initial
Value R/W Description
All 0
0
All 0
1
0
1
0
R
R/W Byte-Selection SRAM Byte Access Selection
R
R/W
R/W
R/W
R/W
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Specifies the WEn and RD/WR signal timing when the byte-
selection SRAM interface is used.
0: Asserts the WEn signal at the read/write timing and
1: Asserts the WEn signal during the read access cycle and
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Number of Access Wait Cycles
Specify the number of cycles that are necessary for
read/write access.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
asserts the RD/WR signal during the write access cycle.
asserts the RD/WR signal at the write timing.
Rev. 1.00, 02/04, page 233 of 804