HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 483

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.6
SCSCR is a 16-bit readable/writable register that enables or disables the SCIF transfer operations
and interrupt requests, and selects the serial clock source.
Bit
15
14
13, 12 
11
Bit Name
TDRQE
RDRQE
TSIE
Serial Control Register (SCSCR)
Initial
Value
0
0
All 0
0
R/W
R/W
R/W
R
R/W
Description
Transmit Data Transmission Request Enable
When transmitting data while TIE = 1 and transmit FIFO data
empty has been generated, transmit FIFO data empty
interrupt or DMA transfer request is selected.
0: Interrupt request to CPU is performed
1: Transmit data transmission request to the DMA is
performed
Receive Data Transmission Request Enable
When receiving data while RIE = 1 and received FIFO data full
is generated, received FIFO data full interrupt or DMA transfer
request is selected.
0: Interrupt request to CPU is performed
1: Transmit data transmission request to the DMA is
performed
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Transmit Data Stop Interrupt Enable
Enables or disables generation of a transmit-data-stop
interrupt when the TSE bit in SCFCR is enabled and the TSF
flag in SCSSR is set to 1.
0: Transmit-data-stop interrupt disabled*
1: Transmit-data-stop interrupt enabled
Note: * The interrupt request is cleared by clearing the TSF
flag to 0 after reading 1 from it or clearing the TSIE bit
to 0.
Rev. 1.00, 02/04, page 445 of 804