HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 331

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

1. 1.5 cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control
2. The bus enable signal is negated at the next falling edge of the clock. The address bus and data
3. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion
Figure 9.33 shows the bus arbitration timing in master mode.
In an original slave device designed by the user, multiple bus accesses are generated continuously
to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh
correctly, the slave device must be designed to release the bus mastership within the refresh
interval time. To achieve this, the LSI instructs the REFOUT pin to request the bus mastership
while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus
mastership is received. If the slave releases the bus, the LSI acquires the bus mastership to
execute the SDRAM refresh.
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
Master and Slave Cooperation: Figure 9.34 shows an example of the master and slave devices.
To control system resources correctly between master and slave devices, the roles of the master
and slave devices must be defined appropriately. The SDRAM must be initialized before using
the devices. To use the standby operation to reduce power consumption, the roles of the master
and slave devices must also be defined appropriately.
This LSI is designed to execute all controls such as initialization, refresh, and standby in a device
in master mode. If a master device and a slave device are connected directly in a two-processor
configuration, the master device performs all processing other than memory access. In this case,
the slave device must not access devices such as an SDRAM that require initialization prior to
device initialization. The following methods can be used to prevent this.
control signals
signals are driven high.
bus are started to be driven at the next rising edge of CKIO.
is at the rising edge of the CKIO where address and data signals are driven.
Other bus
A23 to A0
D15 to D0
BREQ
BACK
CKIO
CSn
Figure 9.33 Bus Arbitration Timing (Master Mode)
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