HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 437

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

15.3.8
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each
bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an
interrupt.
Bit
0
Bit
15
14
13
Bit Name
RFOVF
Bit Name
TDMAE
TCRDYE
TFEMPE
Interrupt Enable Register (SIIER)
0
Initial
Value
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive FIFO Overflow
0: No receive FIFO overflow
1: Receive FIFO overflow
A receive FIFO overflow means that writing has occurred
when the receive FIFO is full.
When a receive FIFO overflow occurs, the SIOF indicates
overflow, and receive data is lost.
•
•
•
Description
Transmit Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The TDREQE bit can be set as transmit
interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
This bit is valid when the RXE bit in SICTR is 1.
When 1 is written to this bit, the contents are cleared.
Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev. 1.00, 02/04, page 399 of 804