HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 11

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

4.4
4.5
Section 5 Cache .................................................................................................177
5.1
5.2
5.3
5.4
Section 6 X/Y Memory......................................................................................191
6.1
6.2
6.3
Section 7 U Memory..........................................................................................195
7.1
7.2
7.3
Exception Processing While DSP Extension Function is Valid........................................ 168
4.4.1
4.4.2
4.4.3
Usage Notes ...................................................................................................................... 175
Features............................................................................................................................. 177
5.1.1
Register Descriptions ........................................................................................................ 179
5.2.1
5.2.2
Operation .......................................................................................................................... 183
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache ................................................................................................... 186
5.4.1
5.4.2
5.4.3
Features............................................................................................................................. 191
Operation .......................................................................................................................... 192
6.2.1
6.2.2
6.2.3
Usage Notes ...................................................................................................................... 193
6.3.1
6.3.2
6.3.3
6.3.4
Features............................................................................................................................. 195
Operation .......................................................................................................................... 196
7.2.1
7.2.2
7.2.3
Usage Notes ...................................................................................................................... 197
Illegal Instruction Exception and Slot Illegal Instruction Exception ................... 168
CPU Address Error .............................................................................................. 168
Exception in Repeat Control Period..................................................................... 168
Cache Structure.................................................................................................... 177
Cache Control Register 1 (CCR1) ....................................................................... 179
Cache Control Register 2 (CCR2) ....................................................................... 180
Searching the Cache............................................................................................. 183
Read Access......................................................................................................... 184
Prefetch Operation ............................................................................................... 184
Write Access ........................................................................................................ 184
Write-Back Buffer ............................................................................................... 185
Coherency of Cache and External Memory ......................................................... 185
Address Array ...................................................................................................... 186
Data Array ........................................................................................................... 187
Usage Examples................................................................................................... 189
Access from CPU................................................................................................. 192
Access from DSP ................................................................................................. 192
Access from I Bus Master Module ...................................................................... 193
Page Conflict ....................................................................................................... 193
Bus Conflict ......................................................................................................... 193
Cache Settings...................................................................................................... 193
Sleep Mode .......................................................................................................... 194
Access from CPU................................................................................................. 196
Access from DSP ................................................................................................. 196
Access from I Bus Master Module ...................................................................... 196
Rev. 1.00, 02/04, page xi of xxxviii