HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 23

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figures
Section 1 Overview
Figure 1.1 Block Diagram of SH7660 ............................................................................................ 8
Figure 1.2 Pin Assignment ............................................................................................................. 9
Section 2 CPU
Figure 2.1 Processing State Transitions........................................................................................ 30
Figure 2.2 Logical Address Space ................................................................................................ 32
Figure 2.3 P4 Area........................................................................................................................ 33
Figure 2.4 Physical Address Space............................................................................................... 34
Figure 2.5 External Address Space and Mounted Space (Area 0) ................................................ 35
Figure 2.6 Register Configuration in Each Processing Mode....................................................... 37
Figure 2.7 General Registers ........................................................................................................ 39
Figure 2.8 System Registers and Program Counter ...................................................................... 40
Figure 2.9 Control Register Configuration ................................................................................... 44
Figure 2.10 Data Format on Memory (Big Endian Mode) ........................................................... 46
Figure 2.11 Data Format on Memory (Little Endian Mode) ........................................................ 46
Section 3 DSP Operating Unit
Figure 3.1 DSP Instruction Format............................................................................................... 74
Figure 3.2 CPU Registers in DSP Mode....................................................................................... 76
Figure 3.3 DSP Register Configuration ........................................................................................ 80
Figure 3.4 DSP Registers and Bus Connections ........................................................................... 97
Figure 3.5 General Registers (DSP Mode) ................................................................................. 100
Figure 3.6 Sample Parallel DSP Instruction Program................................................................. 113
Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions ....................... 115
Figure 3.8 Data Formats ............................................................................................................. 117
Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow........................................................... 118
Figure 3.10 Operation Sequence Example.................................................................................. 120
Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode ........................................ 121
Figure 3.12 DC Bit Generation Examples in Negative Value Mode .......................................... 121
Figure 3.13 DC Bit Generation Examples in Overflow Mode.................................................... 122
Figure 3.14 ALU Integer Arithmetic Operation Flow ................................................................ 123
Figure 3.15 ALU Logical Operation Flow ................................................................................. 125
Figure 3.16 Fixed-Point Multiply Operation Flow ..................................................................... 127
Figure 3.17 Arithmetic Shift Operation Flow............................................................................. 129
Figure 3.18 Logical Shift Operation Flow.................................................................................. 131
Figure 3.19 PDMSB Operation Flow ......................................................................................... 133
Figure 3.20 Rounding Operation Flow ....................................................................................... 135
Figure 3.21 Definition of Rounding Operation........................................................................... 136
Figure 3.22 Local Data Move Instruction Flow.......................................................................... 137
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