HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 732

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

26.5
When ASEMD0 is driven high, the H-UDI pins are function as pins for the JTAG. All boundary
scan cells on this LSI are connected as a single shift register with an input from the TDI pin and an
output from the TDO pin to form the boundary scan register (SDBSR). The TDO and TDI pins of
all LSIs that support the boundary scan function on the board are connected as a single shift
register to form the boundary scan register. This allows wiring between the LSIs on the board and
the mounted conditions of LSIs to be tested.
26.5.1
This LSI supports the three essential instructions defined in the JTAG standard (BYPASS,
SAMPLE/PRELOAD, and EXTEST) and an optional instruction (IDCODE).
1. BYPASS
2. SAMPLE/PRELOAD
Rev. 1.00, 02/04, page 694 of 804
The BYPASS instruction is an essential standard instruction that operates the bypass register.
This instruction shortens the shift path to speed up serial data transfer involving other LSIs on
the printed circuit board. This LSI's system circuits are not affected by execution of this
instruction. The instruction code is B'111.
The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the
boundary scan register, outputs values from the scan path, and loads data onto the scan path.
When this instruction is executing, this LSI's input pin signals are transmitted directly to the
internal circuitry, and internal circuit values are directly output externally from the output pins.
This LSI's system circuits are not affected by execution of this instruction. The instruction
code is B'001.
In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the
internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is
latched into the boundary scan register and read from the scan path. Snapshot latching is
performed in synchronization with the rising of TCK in the Capture-DR state. Snapshot
latching does not affect normal operation of this LSI.
In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary
scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD
operation, when the EXTEST instruction was executed an undefined value would be output
from the output pin until completion of the initial scan sequence (transfer to the output latch)
(with the EXTEST instruction, the parallel output latch value is constantly output to the output
pin).
Boundary Scan
Supported Instructions