HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 564

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.3.7
HHCCAR includes physical addresses in the host controller communication area. The host
controller driver determines the alignment limitation by writing 1 to all bits in the HcHCCA
register and by reading the content of the HcHCCA register. Alignment is determined by checking
the number of 0 in the lower bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7
must always be 0 when they are read. This area is used to retain the control structure and interrupt
table that are accessed by the host controller and host controller driver.
Rev. 1.00, 02/04, page 526 of 804
Bit
1
0
Bit
31 to 8 HCCA
7 to 0
Bit Name
WDH
SO
Bit Name
—
HcHCCA Register (HHCCAR)
Initial
Value
0
0
Initial
Value
All 0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
WriteBack Done Head Interrupt Disable
When this bit is set to 1, an interrupt generation by the
WriteBack Done Head event is masked. When 1 is
written to the WDH bit in the HcInterruptEnable register,
this bit is cleared to 0.
0: This bit is ignored.
1: Disables interrupt generation due to the WriteBack
Scheduling Overrun Interrupt Disable
When this bit is set to 1, an interrupt generation by the
SchedulingOverrun event is masked. When 1 is written to
the SO bit in the HcInterruptEnable register, this bit is
cleared to 0.
0: This bit is ignored.
1: Disables interrupt generation due to the
Description
These bits are physical addresses in the Host Controller
Communication Area.
These bits are always read as 0. The write value should
always be 0. The operation is not guaranteed if 1 is
written to these bits.
Done Head event.
SchedulingOverrun event.