HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 165

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 3.25 Variation of Fixed-Point Multiply Operation
Table 3.26 Correspondence between Operands and Registers
Note: The multiply operations basically generate 32-bit operation results. So when a register
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic. So, the upper
words of each multiplier and multiplicand are input into a MAC unit as shown in figure 3.16. In
the CPU instruction multiply operations, the lower words of both source operands are input into a
MAC unit. The operation result is also different from the CPU’s case. The CPU instruction
multiply operation result is aligned to the LSB of the destination, but the fixed-point multiply
operation result of DSP unit is aligned to the MSB, so that the LSB of the fixed-point multiply
operation result is always 0.
Mnemonic
PMULS
Register
A0
A1
M0
M1
X0
X1
Y0
Y1
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
Function
Signed multiplication
Se

Yes


Yes
Yes
Yes

39
Figure 3.16 Fixed-Point Multiply Operation Flow
31
S
0
39
16
31
Source 1
S
MAC
0
Sf

Yes


Yes

Yes
Yes
Source 1
Se
Destination
39
1
0
31
0
S
Point position
S: Signed bit
16
Source 2
Sf
Rev. 1.00, 02/04, page 127 of 804
Source 2
Ignored
Dg
Yes
Yes
Yes
Yes




0
Destination
Dg