HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 562

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.3.6
Each disable bit in HIDR controls whether to mask an interrupt by an event related to the
HcInterruptStatus register. A hardware interrupt is not requested to the CPU when an event bit in
the HcInterruptStatus register is set and a corresponding bit in the HcInterruptDisable register is
set or the MIE bit in the HcInterruptDisable register is set.
Writing 1 in this register clears the corresponding bit in the HcInterruptEnable register (disable
state), while writing 0 does not change it. When the specified bit is disabled, writing data in which
only the corresponding bit is 1 enables the bit to be disabled independently without checking the
states of other bits.
HIDR is in conjunction with the HcInterruptEnable register which is described before. Therefore
when the specified bit needs to be cleared to 0 (enable state), writing 1 in the corresponding bit in
the HcInterruptEnable register enables the corresponding bit in this register to be automatically
cleared to 0. When this register is read, the current value of the HcInterruptEnable register is
returned.
Rev. 1.00, 02/04, page 524 of 804
Bit
31
30
29 to 7 —
Bit Name
MIE
OC
HcInterruptDisable Register (HIDR)
Initial
Value
0
0
All 0
R/W
R/W
R/W
R
Description
Master Interrupt Disable
When this bit is set to 1, an interrupt generation by the
event specified in another bit in this register is masked.
When 1 is written to the MIE bit in the HcInterruptEnable
register, this bit is cleared to 0.
0: This bit is ignored.
1: Disables interrupt generation due to the event specified
Ownership Change Interrupt Disable
When this bit is set to 1, an interrupt generation by the
Ownership Change event is masked. When 1 is written to
the OC bit in the HcInterruptEnable register, this bit is
cleared to 0.
0: This bit is ignored.
Reserved
These bits are always read as 0. The write value should
always be 0. The operation is not guaranteed if 1 is
written to these bits.
1: Disables interrupt generation due to the Ownership
Change event.
by other bit.