HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 605

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
20.3.5
EPDR0o is a 64-byte 8-bit receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive
data other than setup commands. When data is received normally, EP0oTS in IFR0is set, and the
number of receive bytes is indicated in the EP0o receive data size register. After the data has been
read, setting EP0oRDFN in TRG enables the next packet to be received. This FIFO buffer can be
initialized by means of EP0oCLR in the FIFO clear register (FCLR).
20.3.6
EPDR0s is a data register specifically for endpoint 0 setup command. EPDR0s holds 8-byte
command data sent in the setup stage. However, only the command to be processed by a
microprocessor (firmware) is received. The command data to be processed automatically by this
module is not stored.
When the reception of data in the setup stage starts during read, the previous data is overwritten
unconditionally. When the reception of the next command occurs during command read, the
command reception starts and data read during command read is invalid.
Note: EPDR0s must be read in 8-byte units. If reading is suspended while it is in progress, data
20.3.7
EPDR1 is a 16-byte 8-bit transmit FIFO buffer for endpoint 1. EPDR1 holds one packet of
transmit data for the interrupt transfer of endpoint 1. Transmit data is fixed by writing one packet
of data and setting EP1PKTE in TRG. When an ACK handshake is returned from the host after the
data has been transmitted, EP1TS in IFR0 is set. This FIFO buffer can be initialized by means of
EP1CLR in FCLR.
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
received in the next setup cannot be read successfully.
Bit Name
D7 to D0
Bit Name
D7 to D0
Bit Name
D7 to D0
EP0o Data Register (EPDR0o)
EP0s Data Register (EPDR0s)
EP1 Data Register (EPDR1)
Initial Value
Undefined
Initial Value
Undefined
Initial Value
Undefined
R/W
R
R/W
R
R/W
W
Description
Data register for control-out transfer
Description
Data register for storing the setup command at the
control-out transfer
Description
Data register for endpoint 1 transfer
Rev. 1.00, 02/04, page 567 of 804

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