HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 499

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.11 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit read-only register that indicates the number of data bytes stored in the transmit
FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR).
Bits 14 to 8 show the number of transmit data bytes in SCFTDR, and bits 6 to 0 show the number
of receive data bytes in SCFRDR.
16.3.12 Transmit Data Stop Register (SCTDSR)
SCTDSR is an 8-bit readable/writable register that sets the number of transmit data bytes.
SCTDSR is valid only when the TSE bit in the FIFO control register (SCFCR) is enabled.
Transmit operation is stopped when the number of data bytes set in SCTDSR is transmitted. The
setting value should be H'00 (one byte) to H'FF (256 bytes). This function is only enabled in
asynchronous mode.
SCTDSR is initialized to H'FF.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name

T6
T5
T4
T3
T2
T1
T0

R6
R5
R4
R3
R2
R1
R0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Description
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reserved
This bit is always read as 0.
These bits show the number of untransmitted data bytes in
SCFTDR.
A value of H'00 means that there is no transmit data, and a
value of H'40 means that SCFTDR is full of transmit data.
Reserved
This bit is always read as 0.
These bits show the number of receive data bytes in SCFRDR.
A value of H'00 means that there is no receive data, and a
value of H'40 means that SCFRDR is full of receive data.
Rev. 1.00, 02/04, page 461 of 804