HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 468

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

15.4.10 SPI Mode
SPI-mode operation is selected for the SIOF by the setting in SPICR.
Example of Configuration: Figure 15.21 shows an example of the configuration for SPI-mode
communications.
SPI Operation: The states of operation in SPI mode are described in terms of transmission and
reception in table 15.13. In SPI mode, the data length is fixed to 8 bits and the values of the upper
8 bits of SITDR and SIRDR are the valid data for transmission and reception, respectively.
The only sources of interrupts that should be enabled in SPI-mode transfer are transmit data
transfer request (TDREQ), transmit FIFO empty (TFEMP), receive-data transfer request
(RDREQ), receive-FIFO full (RFFUL), and receive-FIFO overflow (RFOVF). Enabled or
disabled states are selectable by the interrupt enable register (SIIER). Interrupts from other sources
must be disabled at all times.
For the DMA transfer requests, the enabled sources are transmit-data DMA transfer request
(TDMA) and receive-data DMA transfer request (RDMA). Enabled or disabled states are
selectable by the interrupt enable register (SIIER).
In SPI mode, the baud rate is set by SISCR.
Rev. 1.00, 02/04, page 430 of 804
SITDR/SIRDR
Master SPI
Transmit FIFO
Receive FIFO
The shaded part is the data which is transmitted or received.
Baud rate
generator
Figure 15.21 Example of Configuration in SPI Mode
31
Data
24 23
P/S
S/P
MOSI
MISO
SS0
SCK
SS
Slave 0 SPI
0