HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 560

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Rev. 1.00, 02/04, page 522 of 804
Bit
29 to 7 —
6
5
4
3
Bit Name
RHSC
FNO
UE
RD
Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0. The operation is not guaranteed if 1 is
written to these bits.
Root Hub Status Change Interrupt Enable
When this bit is set to 1, an interrupt generation by the
Root Hub Status Change event is enabled. When 1 is
written to the RHSC bit in the HcInterruptDisable register,
this bit is cleared to 0.
0: This bit is ignored.
1: Enables interrupt generation due to the Root Hub
Frame Number Overflow Interrupt Enable
When this bit is set to 1, an interrupt generation by the
Frame Number Overflow event is enabled. When 1 is
written to the FNO bit in the HcInterruptDisable register,
this bit is cleared to 0.
0: This bit is ignored.
1: Enables interrupt generation due to the Frame Number
Unrecoverable Error Interrupt Enable
When this bit is set to 1, an interrupt generation by the
Unrecoverable Error event is enabled. When 1 is written
to the UE bit in the HcInterruptDisable register, this bit is
cleared to 0.
0: This bit is ignored.
1: Enables interrupt generation due to the Unrecoverable
Resume Detected Interrupt Enable
When this bit is set to 1, an interrupt generation by the
Resume Detected event is enabled. When 1 is written to
the RD bit in the HcInterruptDisable register, this bit is
cleared to 0.
0: This bit is ignored.
1: Enables interrupt generation due to the Resume
Status Change event.
Overflow event.
Error event.
Detected event.