HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 387

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
12.2
The WDT has the following two registers. Refer to the section 27, List of Registers, for the details
of the addresses of these registers and the state of registers in each operating mode.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
12.2.1
The watchdog timer counter (WTCNT) is an 8-bit readable/writable register that increments on the
selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an
interrupt in interval timer mode. The WTCNT counter is initialized to H'00 only by a power-on
reset caused by the RESETP pin. Use a word access to write to the WTCNT counter, writing H′5A
in the upper byte. Use a byte access to read the WTCNT.
Note: The WTCNT differs from other registers in the prevention of erroneous writes. See section
12.2.2
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
composed of bits to select the clock used for the count, bits to select the timer mode, overflow
flags and enable bits. The WTCSR register holds its value in an internal reset due to WDT
overflow. The WTCSR register is initialized only by a power-on reset via the RESETP pin.
When used to count the clock settling time for canceling a standby, it retains its value after counter
overflow. Use a word access to write to the WTCSR counter, writing H'A5 in the upper byte. Use
a byte access to read the WTCSR.
Note: The WTCNT differs from other registers in the prevention of erroneous writes. See section
12.2.3, Notes on Register Access, for details.
12.2.3, Notes on Register Access, for details.
Watchdog Timer Control/Status Register (WTCSR)
Register Descriptions
Watchdog Timer Counter (WTCNT)
Rev. 1.00, 02/04, page 349 of 804

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