HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 511

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: Reception continues when a receive error (a framing error or parity error) occurs.
In serial reception, the SCIF operates as described below.
A. The SCIF monitors the communication line, and if 0 of a start bit is detected, performs
B. The received data is stored in SCRSR in LSB-to-MSB order.
C. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
If all the above checks are passed, the receive data is stored in SCFRDR.
D. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-
internal synchronization and starts reception.
a. Stop bit check: the SCIF checks whether the stop bit is 1. If there are two stop bits, only
b. The SCIF checks whether receive data can be transferred from the receive shift register
c. Break check: the SCIF checks that the BRK flag is 0, indicating that the break state is
full interrupt (RXI) request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt (BRI) request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive-data-ready
interrupt (DRI) request is generated.
The vectors of interrupts generated by each factor are the same.
the first is checked.
(SCRSR) to SCFRDR.
not set.
Rev. 1.00, 02/04, page 473 of 804