HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 527

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Initialize SCIF: The communication format should be changed according to the following
procedure after the TE and RE bits are cleared to 0. The transmit shift register (SCTSR) is
initialized by clearing the TE bit to 0. The receive shift register (SCRSR) is initialized by clearing
the RE bit to 0. The contents of the serial status register (SCSSR), transmit FIFO data register
(SCFTDR), and receive FIFO data register (SCFRDR) is retained even when the TE and RE bits
are cleared to 0. The TE bit should be cleared after all transmit data have been transmitted and the
TEND bit in SCSSR has been set to 1. The TE bit can be cleared while the data transmission is in
progress. However, the data go to high-impedance after the TE bit has been cleared to 0. To start
transmission again by setting the TE bit to 1, the SCFTDR should be reset by setting the TFRST
bit in SCFCR to 1.
The external clock should not be halted during the operation including an initialization since the
operation becomes unstable.
Transition to Power-Down Mode: The transitions to software standby mode and module standby
mode should not be made by setting the module standby bit of SCIF during serial transmission and
reception. The transitions to software standby mode and module standby mode should be made
after both TE and RE bits in the serial control register (SCSCR) have been cleared
(transmission/reception disabled).
Transmit/Receive Pin in Transmission/Reception Disabled State: The TxD pin of the SCIF is
in high-impedance state while the TE bit is cleared. The RxD pin is in input fixed state while the
RE bit is cleared. Care is required on dealing a signal line that is connected to the TxD pin. When
the connect destination pin is in input state, connect the pull-up register to a signal line.
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