HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 346

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

10.3.5
IAR is a 32-bit readable/writable register that specifies the initial address of SAR or DAR for
repeating the DMA transfer.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. IAR is undefined at reset and retains the current value in standby or module standby mode.
10.3.6
DMAOR is a 32-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status. DMAOR is undefined at reset and
retains the current value in the standby or module standby mode.
Rev. 1.00, 02/04, page 308 of 804
Bit
31
30
29
28
27
26
Bit Name

CMS1
CMS0

DMA Initial Address Register (IAR)
DMA Operation Register (DMAOR)
Initial
Value
All 0
0
0
All 0
R/W Description
R
R/W
R/W
R
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to this bit, correct operation cannot
be guaranteed.
Cycle Steal Mode Select 1, 0
These bits select either normal mode or intermittent mode in
cycle steal mode.
It is necessary that the bus modes of all channels be set to
cycle steal mode to make the intermittent mode valid.
00: Normal mode
01: Reserved (setting prohibited)
10: Intermittent mode 16
11: Intermittent mode 64
Reserved
These bits are always read as 0. The write value should
always be 0. If 1 is written to these bits, correct operation
cannot be guaranteed.
Executes one DMA transfer in each of 16 clocks of an
external bus clock.
Executes one DMA transfer in each of 64 clocks of an
external bus clock.