HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 663

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

22.3.2
DACR is an 8-bit readable/writable register that controls the DAC operation. DACR is initialized
to H'3F at a reset. Note that DACR is not initialized in software standby or module standby.
22.4
The DAC incorporates two D/A channels that can operate individually.
The DAC executes D/A conversion while analog output is enabled by the D/A control register
(DACR). If the D/A data registers (DADR_0 and DADR_1) are modified, the D/A converter
immediately initiates the new data conversion. When the DAOE1 and DAOE0 bits in the DACR
register are set to 1, D/A conversion results are output.
An example of D/A conversion for channel 0 is shown below. The operation timing is shown in
figure 22.2.
1. Write conversion data to DADR_0.
2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. The results are output after
Bit
7
6
5 to 0 —
the conversion has ended. The output value will be (DADR_0 contents/256) × AVcc.
The conversion results are output continuously until DADR_0 is modified or the DAOE0 bit is
cleared to 0.
Bit Name
DAOE1
DAOE0
D/A Control Register (DACR)
Operation
Initial
Value
0
0
All 1
R/W
R/W
R/W
R
Description
Controls D/A conversion for channel 1 and analog output.
0: D/A conversion for channel 1 and analog output (DA1)
1: D/A conversion for channel 1 and analog output (DA1)
Controls D/A conversion for channel 0 and analog output.
0: D/A conversion for channel 0 and analog output (DA0)
1: D/A conversion for channel 0 and analog output (DA0)
Reserved
These bits are always read as 1. The write value should
always be 1. If 0 is written to these bits, correct operation
cannot be guaranteed.
are enabled
are disabled
are enabled
are disabled
Rev. 1.00, 02/04, page 625 of 804