HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 15

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

14.4 Interrupts........................................................................................................................... 379
14.5 Usage Notes ...................................................................................................................... 380
Section 15 Serial I/O with FIFO (SIOF)............................................................381
15.1 Features............................................................................................................................. 381
15.2 Input/Output Pins .............................................................................................................. 383
15.3 Register Descriptions ........................................................................................................ 384
15.4 Operation .......................................................................................................................... 410
15.5 Usage Notes ...................................................................................................................... 433
Section 16 Serial Communication Interface with FIFO (SCIF) ........................435
16.1 Features............................................................................................................................. 435
16.2 Input/Output Pins .............................................................................................................. 438
16.3 Register Descriptions ........................................................................................................ 439
14.4.1 Status Flag Set Timing......................................................................................... 379
14.4.2 Status Flag Clear Timing ..................................................................................... 379
14.4.3 Interrupt Sources and Priorities ........................................................................... 380
15.3.1 Mode Register (SIMDR)...................................................................................... 384
15.3.2 Control Register (SICTR) .................................................................................... 387
15.3.3 Transmit Data Register (SITDR) ......................................................................... 390
15.3.4 Receive Data Register (SIRDR) .......................................................................... 391
15.3.5 Transmit Control Data Register (SITCR) ............................................................ 392
15.3.6 Receive Control Data Register (SIRCR) ............................................................. 393
15.3.7 Status Register (SISTR)....................................................................................... 394
15.3.8 Interrupt Enable Register (SIIER)........................................................................ 399
15.3.9 FIFO Control Register (SIFCTR) ........................................................................ 401
15.3.10 Clock Select Register (SISCR) ............................................................................ 403
15.3.11 Transmit Data Assign Register (SITDAR) .......................................................... 404
15.3.12 Receive Data Assign Register (SIRDAR)............................................................ 405
15.3.13 Control Data Assign Register (SICDAR) ............................................................ 406
15.3.14 SPI Control Register (SPICR) ............................................................................. 408
15.4.1 Serial Clocks ........................................................................................................ 410
15.4.2 Serial Timing ....................................................................................................... 411
15.4.3 Transfer Data Format........................................................................................... 412
15.4.4 Register Allocation of Transfer Data ................................................................... 413
15.4.5 Control Data Interface ......................................................................................... 416
15.4.6 FIFO..................................................................................................................... 417
15.4.7 Transmit and Receive Procedures........................................................................ 419
15.4.8 Interrupts.............................................................................................................. 424
15.4.9 Transmit and Receive Timing.............................................................................. 426
15.4.10 SPI Mode ............................................................................................................. 430
16.3.1 Receive Shift Register (SCRSR).......................................................................... 440
16.3.2 Receive FIFO Data Register (SCFRDR) ............................................................. 440
Rev. 1.00, 02/04, page xv of xxxviii