HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 638

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

EP3o has two 60-byte FIFOs in maximum, but the user can perform data transmission and read
transmit data without being aware of this dual-FIFO configuration. (In figure 20.16, FIFO sides A
and B are used for description.)
In isochronous transfer, transfer is occurred only once per one frame (1 ms). So, when SOF is
received the FIFO buffer is switched automatically with hardware (the FIFO buffer is switched
automatically at a cycle of 1 ms by hardware if the SOF marker function is enabled even in the
case that SOF cannot be received by error).
FIFO buffers are switched over by the SOF reception. Therefore, the FIFO buffer in which the
USB function module receives the data from the host and the FIFO buffer in which the firmware
reads the receive data have different buffers, and a read and write of FIFO buffer are not
competed. Accordingly, the data written by the firmware is the data received in one frame before.
The buffers of FIFOs are switched over automatically by the SOF reception, so a read of data must
be completed within the frame.
The USB function module receives data from the host after an out-token is received. If there is an
error in the data, set the TF internal flag to 1. If there is no error in the data, set the TS internal flag
to 1. The internal flag (TF, TS) information is automatically modified as IFR0 flag information
(TF, TS) that can be read by the SOF reception from the firmware.
In firmware, first, the processing routine of the isochronous transfer is called by SOF interrupt to
check the time stamp. Then data is read from the FIFO buffer. IFR0 flag information (TS, TF) is
read and decided if the data has an error. The IFR0 flag information at this time represents the
status of the currently readable FIFO buffer.
Rev. 1.00, 02/04, page 600 of 804