HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 567

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

19.3.14 HcFmInterval Register (HFIR)
HFIR includes a 14-bit value indicating the bit time interval of the frame (i.e., between two serial
SOFs) and a 15-bit value indicating the maximum packet size at a full speed that is transmitted
and received by the host controller without causing SchedulingOverrun. The host controller driver
adjusts the frame interval minutely by writing a new value over the current value in each SOF.
Bit
3 to 0
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15, 14
Bit Name
—
Bit Name
FIT
FSMPS14
FSMPS13
FSMPS12
FSMPS11
FSMPS10
FSMPS9
FSMPS8
FSMPS7
FSMPS6
FSMPS5
FSMPS4
FSMPS3
FSMPS2
FSMPS1
FSMPS0
—
0
Initial
Value
All 0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All 0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0. The operation is not guaranteed if 1 is
written to these bits.
Description
Frame Interval Toggle
This bit is toggled by the host controller driver whenever
it loads a new value into the Frame Interval bits.
FSLargest Data Packet
These bits specify a value which is loaded into the
Largest Data Packet Counter at the beginning of each
frame. The counter value expresses the largest data
amount of the bit that can be transmitted and received in
one transaction by the host controller at any given time
without causing SchedulingOverrun. The field value is
calculated by the host controller driver.
Reserved
These bits are always read as 0. The write value should
always be 0. The operation is not guaranteed if 1 is
written to these bits.
Rev. 1.00, 02/04, page 529 of 804