HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 234

• Manufacturer Part Number: HD6417660
• Description: Renesas 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2
7.2.1
The 8/16/32-bit access by the CPU can be performed via the L bus or I bus. Methods for accessing
by the CPU are directly via the L bus from the virtual addresses, and via the I bus from the
physical addresses. As long as a conflict on the page does not occur, access via the L bus is
performed in one cycle. Several cycles are necessary for accessing via the I bus. According to the
CPU operating mode, access from the CPU is as follows:
Privileged mode and privileged DSP mode (SR. MD = 1): The U memory can be accessed by
the CPU from spaces P0 and P2.
User DSP mode (SR.MD = 0 and SR.DSP = 1): The U memory can be accessed by the CPU
from spaces U0 and Uxy.
User mode (SR.MD = 0 and SR.DSP = 0): The U memory can be accessed by the CPU from
space U0.
7.2.2
The U memory can be accessed from the DSP only by a single data transfer instruction. The16/32
-bit access by the DSP can be performed via the L bus or I bus. The access cannot be performed
by an X data transfer instruction and a Y data transfer instruction.
Methods for accessing from the DSP are via the L bus from the virtual addresses, and via the I bus
from the physical addresses. As long as a conflict on the page does not occur, access via the L bus
is performed in one cycle. Several cycles are necessary for accessing via the I bus. According to
the CPU operating mode, access from the CPU is as follows:
Privileged DSP mode (SR. MD = 1 and SR.DSP = 1): The U memory can be accessed by the
DSP from spaces P0 and P2.
User DSP mode (SR.MD = 0 and SR.DSP = 1): The U memory can be accessed by the DSP
from spaces U0 and Uxy.
7.2.3
The U memory is always accessed by I bus master modules such as the DMAC and USBH via the
I bus, which is a physical address bus. The 8/16/32-bit access can be performed by the DMAC and
the 8/32-bit access can be performed by the USBH. When accessing other than the P4 area (A31 to
A29 = B'111), three most significant bits of the address are internally set to B'000 even if the logic
addresses are specified other than P4 area. Therefore, access is performed through I bus.
Rev. 1.00, 02/04, page 196 of 804
Operation
Access from CPU
Access from DSP
Access from I Bus Master Module