HD6417660 RENESAS [Renesas Technology Corp], HD6417660 Datasheet - Page 364

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HD6417660

Manufacturer Part Number
HD6417660
Description
Renesas 32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1. Dual address mode
2. DREQ low level detection
2. Burst Mode
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table
10.9 shows the relationship between request modes and bus modes by DMA transfer category.
Rev. 1.00, 02/04, page 326 of 804
Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode (Dual address,
Figure 10.11 DMA Transfer Example in the Burst Mode (Dual Address, DREQ low level
Once the bus mastership is obtained, the transfer is performed continuously until the transfer
end condition is satisfied. In the external request mode with low level detection of the DREQ
pin, however, when the DREQ pin is driven high, the bus passes to the other bus master after
the DMAC transfer request that has already been accepted ends, even if the transfer end
conditions have not been satisfied.
The burst mode cannot be used for other than CMT00, CMT01, CMT02, and CMT03 when the
on-chip peripheral module is the transfer request source. Figure 10.11 shows DMA transfer
timing in the burst mode.
Bus cycle
DREQ
Bus cycle
DREQ
CPU
CPU
CPU
CPU
DREQ low level detection)
CPU
DMAC DMAC CPU
Read
CPU
detection)
Write
DMAC DMAC DMAC DMAC
Read
More than 16 or 64Bφ
(change by the CPU's condition of using bus)
Write
Read
CPU DMAC DMAC CPU
Write
Read
CPU
Write

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